The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2014
Filed:
Feb. 15, 2011
Chin-chang Hsu, Banqiao, TW;
Wen-ju Yang, Hsinchu, TW;
Hsiao-shu Chao, Baoshan, TW;
Yi-kan Cheng, Taipei, TW;
Lee-chung LU, Taipei, TW;
Chin-Chang Hsu, Banqiao, TW;
Wen-Ju Yang, Hsinchu, TW;
Hsiao-Shu Chao, Baoshan, TW;
Yi-Kan Cheng, Taipei, TW;
Lee-Chung Lu, Taipei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd, Hsin-Chu, TW;
Abstract
Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.