The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2014
Filed:
May. 11, 2010
Applicants:
Sathish Veeraraghavan, Santa Clara, CA (US);
Jaydeep Sinha, Livermore, CA (US);
Inventors:
Sathish Veeraraghavan, Santa Clara, CA (US);
Jaydeep Sinha, Livermore, CA (US);
Assignee:
KLA-Tencor Technologies Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06G 7/48 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5009 (2013.01);
Abstract
A method and system for modeling and analyzing wafer nanotopography data utilizes a nonlinear contact finite element model. Inputs to the model include lithography chuck parameters and site-based geometry data. Outputs from the model include in-plane distortions and out-of-plane distortions, from which defocus and overlay can be derived.
Quick Actions:
Veeraraghavan, Sathish. (2014). Site based quantification of substrate topography and its relation to lithography defocus and overlay (U.S. Patent No. 8768665). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8768665
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile