The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2014
Filed:
Jul. 13, 2012
Konstantin V. Loiko, Austin, TX (US);
Toni D. Van Gompel, Austin, TX (US);
Rode R. Mora, Austin, TX (US);
Michael D. Turner, San Antonio, TX (US);
Brian A. Winstead, Austin, TX (US);
Mark D. Hall, Austin, TX (US);
Konstantin V. Loiko, Austin, TX (US);
Toni D. Van Gompel, Austin, TX (US);
Rode R. Mora, Austin, TX (US);
Michael D. Turner, San Antonio, TX (US);
Brian A. Winstead, Austin, TX (US);
Mark D. Hall, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer () and a dielectric layer () disposed between the substrate and the semiconductor layer, (b) creating a trench () which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure () which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer () which comprises a second material and which is disposed on the bottom of the trench.