The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2014

Filed:

Jun. 07, 2012
Applicants:

Chun Hsiung Tsai, Xinpu Township, Hsinchu County, TW;

Sheng-wen Yu, New Taipei, TW;

De-wei Yu, Ping-Tung, TW;

Inventors:

Chun Hsiung Tsai, Xinpu Township, Hsinchu County, TW;

Sheng-Wen Yu, New Taipei, TW;

De-Wei Yu, Ping-Tung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present disclosure provides a method and system for characterizing a pattern loading effect. A method may include performing a reflectivity measurement on a semiconductor wafer and determining an anneal process technique based on the reflectivity measurement. The determining the anneal process technique may include determining a spatial distance for a reflectivity change using a reflectivity map generated using the reflectivity measurement. This spatial distance is compared with the thermal diffusion length associated with each of the plurality of anneal process techniques. In an embodiment, a thermal profile map and/or a device performance map may be provided.


Find Patent Forward Citations

Tsai, Chun. (2014). Method and system for semiconductor device pattern loading effect characterization (U.S. Patent No. 8753904). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8753904

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