The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2014
Filed:
Dec. 17, 2012
Willy Rachmady, Beaverton, OR (US);
Van H. Le, Portland, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Jessica S. Kachian, Portland, OR (US);
Marc C. French, Forest Grove, OR (US);
Aaron A. Budrevich, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Van H. Le, Portland, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Jessica S. Kachian, Portland, OR (US);
Marc C. French, Forest Grove, OR (US);
Aaron A. Budrevich, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.