The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2014
Filed:
Dec. 06, 2011
Alan B. Botula, Essex Junction, VT (US);
Renata Camillo-castillo, Essex Junction, VT (US);
James S. Dunn, Jericho, VT (US);
Jeffrey P. Gambino, Essex Junction, VT (US);
Douglas B. Hershberger, Essex Junction, VT (US);
Alvin J. Joseph, Essex Junction, VT (US);
Robert M. Rassel, Colchester, VT (US);
Mark E. Stidham, Bloomington, IN (US);
Alan B. Botula, Essex Junction, VT (US);
Renata Camillo-Castillo, Essex Junction, VT (US);
James S. Dunn, Jericho, VT (US);
Jeffrey P. Gambino, Essex Junction, VT (US);
Douglas B. Hershberger, Essex Junction, VT (US);
Alvin J. Joseph, Essex Junction, VT (US);
Robert M. Rassel, Colchester, VT (US);
Mark E. Stidham, Bloomington, IN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.