The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2014
Filed:
Feb. 03, 2012
Hyun-soo Chung, Hwaseong-si, KR;
Jae-shin Cho, Yongin-si, KR;
Dong-ho Lee, Seongnam-si, KR;
Dong-hyeon Jang, Suwon-si, KR;
Seong-deok Hwang, Seoul, KR;
Seung-duk Baek, Hwaseong-si, KR;
Hyun-Soo Chung, Hwaseong-si, KR;
Jae-Shin Cho, Yongin-si, KR;
Dong-Ho Lee, Seongnam-si, KR;
Dong-Hyeon Jang, Suwon-si, KR;
Seong-Deok Hwang, Seoul, KR;
Seung-Duk Baek, Hwaseong-si, KR;
SAMSUNG Electronics Co., Ltd., Suwon-si, KR;
Abstract
Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.