The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8735252 B1

PDF
Full Text
Expired
Date of Patent:
May. 27, 2014

Filed:

Jun. 07, 2012
Applicants:

Weibo Yu, Singapore, SG;

Ming-hsi Yeh, Hsinchu, TW;

Chih-tang Peng, Taipei, TW;

Hao-ming Lien, Hsinchu, TW;

Chao-cheng Chen, Shin-Chu, TW;

Syun-ming Jang, Hsin-Chu, TW;

Inventors:

Weibo Yu, Singapore, SG;

Ming-Hsi Yeh, Hsinchu, TW;

Chih-Tang Peng, Taipei, TW;

Hao-Ming Lien, Hsinchu, TW;

Chao-Cheng Chen, Shin-Chu, TW;

Syun-Ming Jang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.


Find Patent Forward Citations

Yu, Weibo. (2014). Method of semiconductor integrated circuit fabrication (U.S. Patent No. 8735252). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8735252

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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