Compact and accurate wafer topography proximity effect modeling for full chip simulation

Abstract

A method for correcting topography proximity effects (TPE) for an integrated circuit (IC) design is described. This method includes dividing the IC design into a plurality of levels (z-direction). Each level can be decomposed into one or more elementary geometries. These elementary geometries can be top view geometries, cross-sectional geometries, half-plane geometries, geometries with single slope sides, and/or geometries with multiple slope sides. The one or more elementary geometries can be compared to primitives in a library. A transfer matrix can be generated using the matching primitives and the elementary geometries. A disturbance matrix can be calculated based on the transfer matrix. This disturbance matrix can advantageously capture a spectrum of a reflective electric field from a spectrum of an incident electric field. Wave propagation through a photoresist layer can be performed using the disturbance matrix for the plurality of levels. A light intensity for TPE correction can be computed based on the wave propagation.