The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2014

Filed:

Mar. 13, 2012
Applicants:

Ching-te Chuang, New Taipei, TW;

Yin-nien Chen, Hinchu, TW;

Chien-yu Hsieh, Hsinchu, TW;

Ming-long Fan, Taichung, TW;

Pi-ho HU, Hsinchu, TW;

Pin Su, Hsinchu County, TW;

Inventors:

Ching-Te Chuang, New Taipei, TW;

Yin-Nien Chen, Hinchu, TW;

Chien-Yu Hsieh, Hsinchu, TW;

Ming-Long Fan, Taichung, TW;

Pi-Ho Hu, Hsinchu, TW;

Pin Su, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VFinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage.


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