The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2014

Filed:

Jul. 16, 2007
Applicants:

Jay S. Burnham, Franklin, VT (US);

James S. Nakos, Essex Junction, VT (US);

James J. Quinlivan, Essex Junction, VT (US);

Bernie Roque, Jr., Williston, VT (US);

Steven M. Shank, Jericho, VT (US);

Beth A. Ward, Essex Junction, VT (US);

Inventors:

Jay S. Burnham, Franklin, VT (US);

James S. Nakos, Essex Junction, VT (US);

James J. Quinlivan, Essex Junction, VT (US);

Bernie Roque, Jr., Williston, VT (US);

Steven M. Shank, Jericho, VT (US);

Beth A. Ward, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a gate dielectric layer. The method includes: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.


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