The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 15, 2014
Filed:
May. 25, 2012
Jiann-tyng Tzeng, Hsinchu, TW;
Chih-liang Chen, Hsinchu, TW;
Yi-feng Chen, Xinpu Township, TW;
Kam-tou Sio, Hsinchu, TW;
Shang-chih Hsieh, Yangmei, TW;
Helen Shu-hui Chang, Baoshan Township, TW;
Jiann-Tyng Tzeng, Hsinchu, TW;
Chih-Liang Chen, Hsinchu, TW;
Yi-Feng Chen, Xinpu Township, TW;
Kam-Tou Sio, Hsinchu, TW;
Shang-Chih Hsieh, Yangmei, TW;
Helen Shu-Hui Chang, Baoshan Township, TW;
Abstract
An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer.