The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2014

Filed:

Jun. 02, 2011
Applicants:

Tai-su Park, Seoul, KR;

Jung-sup OH, Yongin-si, KR;

Gun-joong Lee, Suwon-si, KR;

Jung-soo an, Suwon-si, KR;

Dong-kyu Lee, Bucheon-si, KR;

Jung-geun Park, Suwon-si, KR;

Jeong-do Ryu, Seoul, KR;

Dong-chan Kim, Anyang-si, KR;

Seong-hoon Jeong, Masan-si, KR;

Si-young Choi, Seongnam-si, KR;

Yu-gyun Shin, Seongnam-si, KR;

Jong-ryeol Yoo, Osan-si, KR;

Jong-hoon Kang, Suwon-si, KR;

Inventors:

Tai-Su Park, Seoul, KR;

Jung-Sup Oh, Yongin-si, KR;

Gun-Joong Lee, Suwon-si, KR;

Jung-Soo An, Suwon-si, KR;

Dong-Kyu Lee, Bucheon-si, KR;

Jung-Geun Park, Suwon-si, KR;

Jeong-Do Ryu, Seoul, KR;

Dong-Chan Kim, Anyang-si, KR;

Seong-Hoon Jeong, Masan-si, KR;

Si-Young Choi, Seongnam-si, KR;

Yu-Gyun Shin, Seongnam-si, KR;

Jong-Ryeol Yoo, Osan-si, KR;

Jong-Hoon Kang, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.


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