The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2014
Filed:
Apr. 13, 2012
Mahbub Rashed, Santa Clara, CA (US);
David Doman, Austin, TX (US);
Dinesh Somasekhar, Portland, OR (US);
Yan Wang, San Jose, CA (US);
Yunfei Deng, Sunnyvale, CA (US);
Navneet Jain, Milpitas, CA (US);
Jongwook Kye, Pleasanton, CA (US);
Ali Keshavarzi, Cupertino, CA (US);
Subramani Kengeri, San Jose, CA (US);
Suresh Venkatesan, Danbury, CT (US);
Mahbub Rashed, Santa Clara, CA (US);
David Doman, Austin, TX (US);
Dinesh Somasekhar, Portland, OR (US);
Yan Wang, San Jose, CA (US);
Yunfei Deng, Sunnyvale, CA (US);
Navneet Jain, Milpitas, CA (US);
Jongwook Kye, Pleasanton, CA (US);
Ali Keshavarzi, Cupertino, CA (US);
Subramani Kengeri, San Jose, CA (US);
Suresh Venkatesan, Danbury, CT (US);
GlobalFoundries Inc., Grand Cayman, KY;
Abstract
An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.