The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2014
Filed:
Mar. 16, 2012
Jason E Cummings, Albany, NY (US);
Lisa F Edge, Albany, NY (US);
Balasubramanian S. Haran, Albany, NY (US);
David V Horak, Albany, NY (US);
Hemanth Jagannathan, Albany, NY (US);
Sanjay Mehta, Albany, NY (US);
Jason E Cummings, Albany, NY (US);
Lisa F Edge, Albany, NY (US);
Balasubramanian S. Haran, Albany, NY (US);
David V Horak, Albany, NY (US);
Hemanth Jagannathan, Albany, NY (US);
Sanjay Mehta, Albany, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfO, AlO, ZrO, HfZrO, and HfSiO. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.