The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2014
Filed:
Apr. 08, 2002
Mark T. Ramsbey, Sunnyvale, CA (US);
Tazrien Kamal, San Jose, CA (US);
Jean Y. Yang, Sunnyvale, CA (US);
Emmanuil Lingunis, San Jose, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Yu Sun, Saratoga, CA (US);
Mark T. Ramsbey, Sunnyvale, CA (US);
Tazrien Kamal, San Jose, CA (US);
Jean Y. Yang, Sunnyvale, CA (US);
Emmanuil Lingunis, San Jose, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Yu Sun, Saratoga, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.