The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2014
Filed:
Jul. 17, 2012
Thomas N. Adam, Slingerlands, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Bruce B. Doris, Brewster, NY (US);
Bala S. Haran, Watervliet, NY (US);
Pranita Kulkarni, Slingerlands, NY (US);
Amlan Majumdar, White Plains, NY (US);
Stefan Schmitz, Ballston Spa, NY (US);
Thomas N. Adam, Slingerlands, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Bruce B. Doris, Brewster, NY (US);
Bala S. Haran, Watervliet, NY (US);
Pranita Kulkarni, Slingerlands, NY (US);
Amlan Majumdar, White Plains, NY (US);
Stefan Schmitz, Ballston Spa, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.