The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2014
Filed:
Dec. 28, 2010
Ching-te Chuang, Taipei County, TW;
Hao-i Yang, Taipei, TW;
Mao-chih Hsia, Kaohsiung, TW;
Wei Hwang, Taipei, TW;
Chia-cheng Chen, Taichung County, TW;
Wei-chiang Shih, Taipei, TW;
Ching-Te Chuang, Taipei County, TW;
Hao-I Yang, Taipei, TW;
Mao-Chih Hsia, Kaohsiung, TW;
Wei Hwang, Taipei, TW;
Chia-Cheng Chen, Taichung County, TW;
Wei-Chiang Shih, Taipei, TW;
Faraday Technology Corp., Science-Based Indusrial Park, Hsin-Chu, TW;
National Chiao Tung University, Hsinchu, TW;
Abstract
A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.