The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2014

Filed:

May. 20, 2011
Applicants:

Andrew Ritenour, Colfax, NC (US);

David C. Sheridan, Starkville, MS (US);

Inventors:

Andrew Ritenour, Colfax, NC (US);

David C. Sheridan, Starkville, MS (US);

Assignee:

Power Integrations, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 31/0312 (2006.01);
U.S. Cl.
CPC ...
Abstract

A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 μm to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.


Find Patent Forward Citations

Ritenour, Andrew. (2014). Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making (U.S. Patent No. 8659057). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8659057

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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