The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2014
Filed:
Feb. 08, 2012
Cheng-cheng Kuo, Baoshan Township, Hsinchu County, TW;
Ching-che Tsai, Zhubei, TW;
Tzu-chun Lo, New Taipei, TW;
Chih-wei Hsu, Zhubei, TW;
Hua-tai Lin, Hsinchu, TW;
Tsai-sheng Gau, Hsinchu, TW;
Wen-chun Huang, Tainan, TW;
Chih-shiang Chou, Pingzhen, TW;
Hsin-chang Lee, Hsin-Chu Xian, TW;
Kuei Shun Chen, Hsin-Chu, TW;
Cheng-Cheng Kuo, Baoshan Township, Hsinchu County, TW;
Ching-Che Tsai, Zhubei, TW;
Tzu-Chun Lo, New Taipei, TW;
Chih-Wei Hsu, Zhubei, TW;
Hua-Tai Lin, Hsinchu, TW;
Tsai-Sheng Gau, Hsinchu, TW;
Wen-Chun Huang, Tainan, TW;
Chih-Shiang Chou, Pingzhen, TW;
Hsin-Chang Lee, Hsin-Chu Xian, TW;
Kuei Shun Chen, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.