The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2014
Filed:
Mar. 24, 2011
Chuan Lin, Cupertino, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Bradley Marc Davis, Mountain View, CA (US);
Lei Xue, Milpitas, CA (US);
Simon S. Chan, Saratoga, CA (US);
Kenichi Ohtsuka, Sunnyvale, CA (US);
Angela T. Hui, Fremont, CA (US);
Scott Allan Bell, San Jose, CA (US);
Chuan Lin, Cupertino, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Bradley Marc Davis, Mountain View, CA (US);
Lei Xue, Milpitas, CA (US);
Simon S. Chan, Saratoga, CA (US);
Kenichi Ohtsuka, Sunnyvale, CA (US);
Angela T. Hui, Fremont, CA (US);
Scott Allan Bell, San Jose, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.