The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2014
Filed:
Dec. 11, 2009
Kazuhiro Fujikawa, Osaka, JP;
Hideto Tamaso, Osaka, JP;
Shin Harada, Osaka, JP;
Yasuo Namikawa, Osaka, JP;
Kazuhiro Fujikawa, Osaka, JP;
Hideto Tamaso, Osaka, JP;
Shin Harada, Osaka, JP;
Yasuo Namikawa, Osaka, JP;
Sumitomo Electric Industries, Ltd., Osaka-shi, JP;
Abstract
A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w) in the direction along the upper surface greater than a width (w) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.