The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2014
Filed:
Apr. 10, 2012
Robert R. Arelt, Pleasant Valley, NY (US);
Jeanne P. S. Bickford, Essex Junction, VT (US);
Andrew D. Huber, Poughkeepsie, NY (US);
Gustavo E. Tellez, Essex Junction, VT (US);
Karl W. Vinson, Jericho, VT (US);
Tina Wagner, Newburgh, NY (US);
Robert R. Arelt, Pleasant Valley, NY (US);
Jeanne P. S. Bickford, Essex Junction, VT (US);
Andrew D. Huber, Poughkeepsie, NY (US);
Gustavo E. Tellez, Essex Junction, VT (US);
Karl W. Vinson, Jericho, VT (US);
Tina Wagner, Newburgh, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias.