The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2014
Filed:
Oct. 12, 2012
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Chi-Feng Lin, Hsin-Chu, TW;
Yu-Wei Chou, Hsin-Chu, TW;
Wen-Cheng Huang, Changhua, TW;
Cheng-I Huang, Hsin-Chu, TW;
Ching-Hua Hsieh, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Methods for optimizing conductor patterns for conductors formed by ECP and CMP processes. A method includes receiving layout data for an IC design where electrochemical plating (ECP) processes form patterned conductors in at least one metal layer over a semiconductor wafer; determining from the received layout data a global effects factor corresponding to a global pattern density; determining layout effects factors for unit grid areas corresponding to the pattern density of the at least one metal layer within the unit grid areas, determining local effects factors for each unit grid area; using a computing device, executing an ECP simulator using at least one of the global effects factor and the local effects factors, and using the layout effects factor; outputting an predicted post-ECP hump data map from the ECP simulator; and if indicated by a threshold comparison, modifying the layout data.