The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2013
Filed:
Jun. 14, 2012
Rabindra N. Das, Vestal, NY (US);
Frank D. Egitto, Binghamton, NY (US);
John M. Lauffer, Waverly, NY (US);
How T. Lin, Vestal, NY (US);
Rabindra N. Das, Vestal, NY (US);
Frank D. Egitto, Binghamton, NY (US);
John M. Lauffer, Waverly, NY (US);
How T. Lin, Vestal, NY (US);
Endicott Interconnect Technologies, Inc., Endicott, NY (US);
Abstract
A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor 'core' results. This 'core' may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art.