The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2013

Filed:

Jun. 28, 2012
Applicants:

Chin-cheng Kuo, Taoyuan, TW;

Wei-yi HU, Zhubei, TW;

Jui-feng Kuan, Zhubei, TW;

Yi-kan Cheng, Taipei, TW;

Inventors:

Chin-Cheng Kuo, Taoyuan, TW;

Wei-Yi Hu, Zhubei, TW;

Jui-Feng Kuan, Zhubei, TW;

Yi-Kan Cheng, Taipei, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.


Find Patent Forward Citations

Kuo, Chin-Cheng. (2013). Method of circuit design yield analysis (U.S. Patent No. 8601416). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8601416

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