The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2013

Filed:

Sep. 07, 2011
Applicants:

Donghua Liu, Shanghai, CN;

Wensheng Qian, Shanghai, CN;

Inventors:

Donghua Liu, Shanghai, CN;

Wensheng Qian, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0328 (2006.01); H01L 31/0336 (2006.01); H01L 31/072 (2012.01); H01L 31/109 (2006.01); H01L 29/167 (2006.01); H01L 29/207 (2006.01); H01L 29/227 (2006.01); H01L 31/0288 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.


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