The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2013

Filed:

Aug. 29, 2012
Applicants:

Ching-te Chuang, New Taipei, TW;

Shyh-jye Jou, Hsinchu County, TW;

Geng-cing Lin, Taipei, TW;

Shao-cheng Wang, Kaohsiung, TW;

Yi-wei Lin, New Taipei, TW;

Ming-chien Tsai, Kaohsiung, TW;

Wei-chiang Shih, Taipei, TW;

Nan-chun Lien, Taipei, TW;

Kuen-di Lee, Kinmen County, TW;

Jyun-kai Chu, Hsinchu County, TW;

Inventors:

Ching-Te Chuang, New Taipei, TW;

Shyh-Jye Jou, Hsinchu County, TW;

Geng-Cing Lin, Taipei, TW;

Shao-Cheng Wang, Kaohsiung, TW;

Yi-Wei Lin, New Taipei, TW;

Ming-Chien Tsai, Kaohsiung, TW;

Wei-Chiang Shih, Taipei, TW;

Nan-Chun Lien, Taipei, TW;

Kuen-Di Lee, Kinmen County, TW;

Jyun-Kai Chu, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.


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