The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2013
Filed:
Feb. 02, 2012
André P. Labonté, Scarborough, ME (US);
Richard S. Wise, Ridgefield, CT (US);
Ying LI, Ridgefield, CT (US);
Brett H. Engel, Hopewell Junction, NY (US);
André P. Labonté, Scarborough, ME (US);
Richard S. Wise, Ridgefield, CT (US);
Ying Li, Ridgefield, CT (US);
Brett H. Engel, Hopewell Junction, NY (US);
GLOBALFOUNDRIES, Inc., Grand Cayman, KY;
Abstract
An integrated circuit having a mis-alignment tolerant electrical contact is formed by providing a semiconductor containing substrate over which is a first FET gate laterally bounded by a first dielectric region, replacing an upper portion of the first FET gate with a second dielectric region, applying a mask having an opening extending partly over an adjacent source or drain contact region of the substrate and over a part of the second dielectric region above the first FET gate, forming an opening through the first dielectric region extending to the contact region and the part of the second dielectric region, and filling the opening with a conductor making electrical connection with the contact region but electrically insulated from the first FET gate by the second dielectric region. A further FET gate may also be provided having an electrical contact thereto formed separately from the source-drain contact.