The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2013
Filed:
Jul. 12, 2012
Yan Xun Xue, Los Gatos, CA (US);
Hamza Yilmaz, Saratoga, CA (US);
Yueh-se Ho, Sunnyvale, CA (US);
Jun LU, San Jose, CA (US);
Ping Huang, Songjiang, CN;
Lei Shi, Songjiang, CN;
Lei Duan, Songjiang, CN;
Yuping Gong, Songjiang, CN;
Yan Xun Xue, Los Gatos, CA (US);
Hamza Yilmaz, Saratoga, CA (US);
Yueh-Se Ho, Sunnyvale, CA (US);
Jun Lu, San Jose, CA (US);
Ping Huang, Songjiang, CN;
Lei Shi, Songjiang, CN;
Lei Duan, Songjiang, CN;
Yuping Gong, Songjiang, CN;
Alpha & Omega Semiconductor, Inc., Sunnyvale, CA (US);
Abstract
A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.