The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2013

Filed:

Sep. 25, 2010
Applicants:

Xia an, Beijing, CN;

Yue Guo, Beijing, CN;

Quanxin Yun, Beijing, CN;

RU Huang, Beijing, CN;

Xing Zhang, Beijing, CN;

Inventors:

Xia An, Beijing, CN;

Yue Guo, Beijing, CN;

Quanxin Yun, Beijing, CN;

Ru Huang, Beijing, CN;

Xing Zhang, Beijing, CN;

Assignee:

Peking University, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein the ions implanted in the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion implantation process. According to the method for fabricating a semiconductor device, through the implantation of silicon impurities, appropriate stress may be introduced into the germanium channel effectively by the mismatch of lattices in the source and drain regions, so that the mobility of electrons in the channel is enhanced and the performance of the device is improved.


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