The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2013
Filed:
Jun. 29, 2012
Su-chen Lai, Hsinchu, TW;
Ming-yuan Wu, Hsinchu, TW;
Kong-beng Thei, Pao-Shan Villiage, TW;
Hak-lay Chuang, Hsinchu, TW;
Chiung-han Yeh, Tainan, TW;
Hong-dyi Chang, Taipei, TW;
Kuo Cheng-cheng, Baoshan Township, Hsinchu County, TW;
Chien-hung Wu, Tainan, TW;
Tzung-chi Lee, Hsin Banciao, TW;
Su-Chen Lai, Hsinchu, TW;
Ming-Yuan Wu, Hsinchu, TW;
Kong-Beng Thei, Pao-Shan Villiage, TW;
Hak-Lay Chuang, Hsinchu, TW;
Chiung-Han Yeh, Tainan, TW;
Hong-Dyi Chang, Taipei, TW;
Kuo Cheng-Cheng, Baoshan Township, Hsinchu County, TW;
Chien-Hung Wu, Tainan, TW;
Tzung-Chi Lee, Hsin Banciao, TW;
Other;
Abstract
A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.