The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2013

Filed:

Apr. 22, 2010
Applicants:

Charles T. Black, New York, NY (US);

Matthew E. Colburn, Hopewell Junction, NY (US);

Timothy J. Dalton, Ridgefield, CT (US);

Daniel C. Edelstein, White Plains, NY (US);

Wai-kin LI, Beacon, NY (US);

Anthony K. Stamper, Williston, VT (US);

Haining S. Yang, Wappingers Falls, NY (US);

Inventors:

Charles T. Black, New York, NY (US);

Matthew E. Colburn, Hopewell Junction, NY (US);

Timothy J. Dalton, Ridgefield, CT (US);

Daniel C. Edelstein, White Plains, NY (US);

Wai-Kin Li, Beacon, NY (US);

Anthony K. Stamper, Williston, VT (US);

Haining S. Yang, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/5256 (2006.01); H01L 23/5329 (2006.01); H01L 21/7682 (2006.01);
U.S. Cl.
CPC ...
Abstract

Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.


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