The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8513675 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 20, 2013

Filed:

May. 21, 2012
Applicants:

David C. Sheridan, Starkville, MS (US);

Andrew P. Ritenour, Starkville, MS (US);

Inventors:

David C. Sheridan, Starkville, MS (US);

Andrew P. Ritenour, Starkville, MS (US);

Assignee:

Power Integrations, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/24 (2006.01); H01L 49/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.


Find Patent Forward Citations

Sheridan, David. (2013). Vertical junction field effect transistors having sloped sidewalls and methods of making (U.S. Patent No. 8513675). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8513675

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