The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2013
Filed:
Nov. 29, 2011
Yonggen He, Beijing, CN;
Jingang Wu, Beijing, CN;
Haibiao Yao, Beijing, CN;
Semiconductor Manufacturing International Corporation, Beijing, CN;
Abstract
A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension.