The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2013
Filed:
Sep. 24, 2010
Rohan N. Akolkar, Hillsboro, OR (US);
Sridhar Balakrishnan, Rio Rancho, NM (US);
James S. Clarke, Hillsboro, OR (US);
Christopher J. Jezewski, Hillsboro, OR (US);
Philip Yashar, Portland, OR (US);
Rohan N. Akolkar, Hillsboro, OR (US);
Sridhar Balakrishnan, Rio Rancho, NM (US);
James S. Clarke, Hillsboro, OR (US);
Christopher J. Jezewski, Hillsboro, OR (US);
Philip Yashar, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.