The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 2013
Filed:
Jul. 17, 2012
Jeong-do Ryu, Seoul, KR;
Si-young Choi, Gyeonggi-do, KR;
Yu-gyun Shin, Gyeonggi-do, KR;
Tai-su Park, Gyeonggi-do, KR;
Dong-chan Kim, Gyeonggi-do, KR;
Jong-ryeol Yoo, Gyeonggi-do, KR;
Seong-hoon Jeong, Gyeongsangnam-do, KR;
Jong-hoon Kang, Gyeonggi-do, KR;
Jeong-Do Ryu, Seoul, KR;
Si-Young Choi, Gyeonggi-do, KR;
Yu-Gyun Shin, Gyeonggi-do, KR;
Tai-Su Park, Gyeonggi-do, KR;
Dong-Chan Kim, Gyeonggi-do, KR;
Jong-Ryeol Yoo, Gyeonggi-do, KR;
Seong-Hoon Jeong, Gyeongsangnam-do, KR;
Jong-Hoon Kang, Gyeonggi-do, KR;
Abstract
Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.