The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2013

Filed:

Mar. 10, 2010
Applicants:

Kunal Parekh, Boise, ID (US);

David Hwang, Boise, ID (US);

Wen Kuei Huang, Boise, ID (US);

Kuo Chen Wang, Chiayi, TW;

Ching Kai Lin, Boise, ID (US);

Inventors:

Kunal Parekh, Boise, ID (US);

David Hwang, Boise, ID (US);

Wen Kuei Huang, Boise, ID (US);

Kuo Chen Wang, Chiayi, TW;

Ching Kai Lin, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4Farchitecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.


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