The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2013
Filed:
Jun. 20, 2011
Kensaku Yamamoto, Toyokawa, JP;
Naohiro Suzuki, Anjo, JP;
Hidefumi Takaya, Miyoshi, JP;
Masahiro Sugimoto, Toyota, JP;
Jun Morimoto, Nisshin, JP;
Narumasa Soejima, Seto, JP;
Tsuyoshi Ishikawa, Nisshin, JP;
Yukihiko Watanabe, Nagoya, JP;
Kensaku Yamamoto, Toyokawa, JP;
Naohiro Suzuki, Anjo, JP;
Hidefumi Takaya, Miyoshi, JP;
Masahiro Sugimoto, Toyota, JP;
Jun Morimoto, Nisshin, JP;
Narumasa Soejima, Seto, JP;
Tsuyoshi Ishikawa, Nisshin, JP;
Yukihiko Watanabe, Nagoya, JP;
DENSO CORPORATION, Kariya, JP;
Toyota Jidosha Kabushiki Kaisha, Aichi-pref., JP;
Abstract
A semiconductor device includes a semiconductor substrate and an electric field terminal part. The semiconductor substrate includes a substrate, a drift layer disposed on a surface of the substrate, and a base layer disposed on a surface of the drift layer. The semiconductor substrate is divided into a cell region in which a semiconductor element is disposed and a peripheral region that surrounds the cell region. The base region has a bottom face located on a same plane throughout the cell region and the peripheral region and provides an electric field relaxing layer located in the peripheral region. The electric field terminal part surrounds the cell region and a portion of the electric field relaxing layer and penetrates the electric field relaxing layer from a surface of the electric field relaxing layer to the drift layer.