The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2013

Filed:

Apr. 13, 2011
Applicants:

Jong-wan Choi, Suwon-si, KR;

Wan-sik Hwang, Hwaseong-si, KR;

Gil-heyun Choi, Gangnam-gu, KR;

Eunkee Hong, Seongnam-si, KR;

Ju-seon Goo, Suwon-si, KR;

Bo-young Lee, Hwaseong-si, KR;

Inventors:

Jong-wan Choi, Suwon-si, KR;

Wan-sik Hwang, Hwaseong-si, KR;

Gil-heyun Choi, Gangnam-gu, KR;

Eunkee Hong, Seongnam-si, KR;

Ju-seon Goo, Suwon-si, KR;

Bo-young Lee, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.


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