The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2013
Filed:
May. 23, 2011
Fujio Masuoka, Tokyo, JP;
Hiroki Nakamura, Tokyo, JP;
Shintaro Arai, Tokyo, JP;
Tomohiko Kudo, Tokyo, JP;
Yu Jiang, Tokyo, JP;
King-jien Chui, Tokyo, JP;
Yisuo LI, Tokyo, JP;
Xiang LI, Singapore, SG;
Zhixian Chen, Singapore, SG;
Nansheng Shen, Singapore, SG;
Vladimir Bliznetsov, Singapore, SG;
Kavitha Devi Buddharaju, Singapore, SG;
Navab Singh, Singapore, SG;
Fujio Masuoka, Tokyo, JP;
Hiroki Nakamura, Tokyo, JP;
Shintaro Arai, Tokyo, JP;
Tomohiko Kudo, Tokyo, JP;
Yu Jiang, Tokyo, JP;
King-Jien Chui, Tokyo, JP;
Yisuo Li, Tokyo, JP;
Xiang Li, Singapore, SG;
Zhixian Chen, Singapore, SG;
Nansheng Shen, Singapore, SG;
Vladimir Bliznetsov, Singapore, SG;
Kavitha Devi Buddharaju, Singapore, SG;
Navab Singh, Singapore, SG;
Unisantis Electronics Singapore Pte Ltd., Peninsula Plaza, SG;
Abstract
The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.