The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2013
Filed:
Sep. 19, 2007
John C. Arnold, North Chatham, NY (US);
Griselda Bonilla, Fishkill, NY (US);
William J. Cote, Poughquag, NY (US);
Geraud Dubois, Los Gatos, CA (US);
Daniel C. Edelstein, White Plains, NY (US);
Alfred Grill, White Plains, NY (US);
Elbert Huang, Carmel, NY (US);
Robert D. Miller, San Jose, CA (US);
Satya V. Nitta, Poughquag, NY (US);
Sampath Purushothaman, Yorktown Heights, NY (US);
E. Todd Ryan, Clifton Park, NY (US);
Muthumanickam Sankarapandian, Niskayuna, NY (US);
Terry A. Spooner, Clifton Park, NY (US);
Willi Volksen, San Jose, CA (US);
John C. Arnold, North Chatham, NY (US);
Griselda Bonilla, Fishkill, NY (US);
William J. Cote, Poughquag, NY (US);
Geraud Dubois, Los Gatos, CA (US);
Daniel C. Edelstein, White Plains, NY (US);
Alfred Grill, White Plains, NY (US);
Elbert Huang, Carmel, NY (US);
Robert D. Miller, San Jose, CA (US);
Satya V. Nitta, Poughquag, NY (US);
Sampath Purushothaman, Yorktown Heights, NY (US);
E. Todd Ryan, Clifton Park, NY (US);
Muthumanickam Sankarapandian, Niskayuna, NY (US);
Terry A. Spooner, Clifton Park, NY (US);
Willi Volksen, San Jose, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Advanced Micro Devices, Inc., Austin, TX (US);
Abstract
Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.