The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2013
Filed:
Dec. 02, 2010
Jun Yuan, Fishkill, NY (US);
Dechao Guo, Wappingers Falls, NY (US);
Kwong Hon Wong, Wappingers Falls, NY (US);
Yanfeng Wang, Fishkill, NY (US);
Gan Wang, Fishkill, NY (US);
Jun Yuan, Fishkill, NY (US);
Dechao Guo, Wappingers Falls, NY (US);
Kwong Hon Wong, Wappingers Falls, NY (US);
Yanfeng Wang, Fishkill, NY (US);
Gan Wang, Fishkill, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming a semiconductor device is provided that includes forming a replacement gate structure on portion a substrate, wherein source regions and drain regions are formed on opposing sides of the portion of the substrate that the replacement gate structure is formed on. An intralevel dielectric is formed on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the substrate. A high-k dielectric spacer is formed on sidewalls of the opening, and a gate dielectric is formed on the exposed portion of the substrate. Contacts are formed through the intralevel dielectric layer to at least one of the source region and the drain region, wherein the etch that provides the opening for the contacts is selective to the high-k dielectric spacer and the high-k dielectric capping layer.