The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2013
Filed:
Mar. 08, 2010
Roger A. Booth, Jr., Wappingers Falls, NY (US);
Kangguo Cheng, Guilderland, NY (US);
Rainer Loesing, Newburgh, NY (US);
Chengwen Pei, Danbury, CT (US);
Xiaojun Yu, Beacon, NY (US);
Roger A. Booth, Jr., Wappingers Falls, NY (US);
Kangguo Cheng, Guilderland, NY (US);
Rainer Loesing, Newburgh, NY (US);
Chengwen Pei, Danbury, CT (US);
Xiaojun Yu, Beacon, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance. In a variation thereof, an electrical fuse is formed which includes a continuous silicide region through which a current can be passed to blow the fuse. Some of the steps of fabricating the poly resistor or the electrical fuse can be employed simultaneously in fabricating metal gate field effect transistors (FETs) on the same substrate.