The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2013

Filed:

Jan. 10, 2012
Applicants:

Yoshiaki Fukuzumi, Yokohama, JP;

Hideaki Aochi, Kawasaki, JP;

Masaru Kito, Kuwana, JP;

Kiyotaka Miyano, Tokyo, JP;

Shinji Mori, Yokohama, JP;

Ichiro Mizushima, Yokohama, JP;

Inventors:

Yoshiaki Fukuzumi, Yokohama, JP;

Hideaki Aochi, Kawasaki, JP;

Masaru Kito, Kuwana, JP;

Kiyotaka Miyano, Tokyo, JP;

Shinji Mori, Yokohama, JP;

Ichiro Mizushima, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/01 (2006.01); H01L 27/12 (2006.01); H01L 31/0392 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2006.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
Abstract

According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion. The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.


Find Patent Forward Citations

Fukuzumi, Yoshiaki. (2013). Semiconductor memory device having a circuit formed on a single crystal semiconductor layer with varied germanium concentration (U.S. Patent No. 8476708). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8476708

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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