The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2013

Filed:

Feb. 18, 2011
Applicants:

Dumitru Sdrulla, Bend, OR (US);

Duane Edward Levine, Bend, OR (US);

James M. Katana, Bend, OR (US);

Martin David Birch, Louisville, CO (US);

Inventors:

Dumitru Sdrulla, Bend, OR (US);

Duane Edward Levine, Bend, OR (US);

James M. Katana, Bend, OR (US);

Martin David Birch, Louisville, CO (US);

Assignee:

Microsemi Corporation, Bend, OR (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
Abstract

A high voltage power semiconductor device includes high reliability-high voltage junction termination with a charge dissipation layer. An active device area is surrounded by a junction termination structure including one or more regions of a polarity opposite the substrate polarity. A tunneling oxide layer overlays the junction termination area surrounding the active device area in contact with the silicon substrate upper surface. A layer of undoped polysilicon overlays the tunneling oxide layer and spans the junction termination area, with connections to an outer edge of the junction termination structure and to a grounded electrode inside of the active area. The tunneling oxide layer has a thickness that permits hot carriers formed at substrate upper surface to pass through the tunneling oxide layer into the undoped polysilicon layer to be dissipated but sufficient to mitigate stacking faults at the silicon surface.


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