The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2013
Filed:
May. 22, 2012
Shih-hung Tsai, Tainan, TW;
Ssu-i Fu, Kaohsiung, TW;
Chien-liang Lin, Taoyuan County, TW;
Ying-tsung Chen, Kaohsiung, TW;
Ted Ming-lang Guo, Tainan, TW;
Chin-cheng Chien, Tainan, TW;
Chien-ting Lin, Hsinchu, TW;
Wen-tai Chiang, Tainan, TW;
Shih-Hung Tsai, Tainan, TW;
Ssu-I Fu, Kaohsiung, TW;
Chien-Liang Lin, Taoyuan County, TW;
Ying-Tsung Chen, Kaohsiung, TW;
Ted Ming-Lang Guo, Tainan, TW;
Chin-Cheng Chien, Tainan, TW;
Chien-Ting Lin, Hsinchu, TW;
Wen-Tai Chiang, Tainan, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method of forming fin structure in integrated circuit comprising the steps of forming a plurality of fin structures on a substrate, covering an insulating layer on said substrate, performing a planarization process to expose mask layers, performing a wet etching process to etch said insulating layer, thereby exposing a part of the sidewall of said mask layer, removing said mask layer, and performing a dry etching process to remove pad layer and a part of said insulating layer, thereby exposing the top surface and a part of sidewall of said fin structures.