The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2013

Filed:

Nov. 12, 2010
Applicants:

Yu-fong Huang, Tainan, TW;

Tzung-ting Han, Yilan, TW;

Wen-pin LU, Chupei, TW;

Inventors:

Yu-Fong Huang, Tainan, TW;

Tzung-Ting Han, Yilan, TW;

Wen-Pin Lu, Chupei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSi), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.


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