The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2013
Filed:
May. 25, 2011
Brian R. Bennett, Arlington, VA (US);
John Bradley Boos, Springfield, VA (US);
Mario Ancona, Alexandria, VA (US);
James G. Champlain, Alexandria, VA (US);
Nicolas a Papanicolaou, Potomac, MD (US);
Brian R. Bennett, Arlington, VA (US);
John Bradley Boos, Springfield, VA (US);
Mario Ancona, Alexandria, VA (US);
James G. Champlain, Alexandria, VA (US);
Nicolas A Papanicolaou, Potomac, MD (US);
The United States of America, as represented by the Secretary of the Navy, Washington, DC (US);
Abstract
A complementary metal oxide semiconductor (CMOS) device in which a single InGaSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InGaSb layer is part of a heterostructure that includes a Te-delta doped AlGaSb layer above the InGaSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlGaSb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlGaSb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InGaSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.