The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2013
Filed:
May. 25, 2012
Chin-chang Hsu, Banqiao, TW;
Hunglung Lin, Hsinchu, TW;
Wen-ju Yang, Hsinchu, TW;
Hsiao-shu Chao, Baoshan Township, TW;
Yi-kan Cheng, Taipei, TW;
Chin-Chang Hsu, Banqiao, TW;
HungLung Lin, Hsinchu, TW;
Wen-Ju Yang, Hsinchu, TW;
Hsiao-Shu Chao, Baoshan Township, TW;
Yi-Kan Cheng, Taipei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to a method and apparatus for identifying pre-coloring violations and for providing hints and/or warnings to a designer to eliminate the pre-coloring violations. In some embodiments, the method is performed by identifying G0-spaces within a double patterning technology (DPT) layer, of an integrated chip (IC) layout, having a plurality of pre-colored shapes. Violation paths extending between the pre-colored shapes are identified based upon the G0-spaces. Good paths (i.e., paths that will not cause a violation) and bad paths (i.e., paths that will cause a violation) between the pre-colored shapes are also identified. Hints and/or warnings are generated based upon the identified good and bad paths, wherein the hints and/or warnings provide guidance to eliminate the violation paths and develop a violation free IC layout.